1. Field of the Invention
The present invention relates to a digital PLL circuit and to a clock generator wherein the digital PLL circuit is included, and relates in particular to a reduction in the current consumption by the digital PLL circuit.
2. Description of the Related Art
FIG. 1 is a diagram illustrating an example relevant to a reduction in the current consumption by a semiconductor apparatus that includes a digital PLL circuit. For the arrangement shown in FIG. 1, Japanese Patent Laid-Open No. 2002-135237, for example, should be referred to. While referring to FIG. 1, a switch is provided for the input/output unit of a digital PLL circuit, and to reduce the current consumption, the digital PLL circuit is isolated from the other circuits by using a SLEEP signal, or is halted when not in use.
Further, when only the current consumption by the digital PLL circuit is to be reduced, a technique is employed whereby a digital processing speed can be decreased. FIG. 2 is a diagram depicting an example of the use of the technique, for which Japanese Patent Laid-Open No. H05-235751(1993), for example, should be referred to.
However, the arrangement disclosed in Japanese Patent Laid-Open No. 2002-135237 is employed for reducing current consumption for an entire device, and is not provided for reducing only the current consumption by a PLL circuit. Further, the technique described in Japanese Patent Laid-Open No. H05-235751(1993) relates to a digital signal processing PLL circuit that extracts a clock from digital audio data, for example, and that reduces the number of digital data operations to obtain a lower current consumption than the other conventional technique does. This method, therefore, is not satisfactory for the reduction of the current consumed by a PLL circuit alone.